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SHAKTI Processor Program

The SHAKTI processor program at IIT-Madras has been kind of an official program for a while now but has not been  publicized since we figured it made more sense to wait till we had some code in place.We finally made our code code-line public yesterday, so do go take a look at

 bitbucket.org/casl/shakti_public

 Our RapidIO interconnect program and our lightstor SSD controller are also in the casl directory. 

 Currently we have released a 64 bit dual issue, OO core. This is the I-Class core, one of the six+ families of cores we plan to release. See 

 http://rise.cse.iitm.ac.in/shakti.html

This is just a base core and not a full SoC. A brief run-down of the features of the core
  1. 64-bit, dual issue variant of Shakti processor family. Features a pipeline of depth of 8 stages. The 8 stages of the pipeline are - Fetch, Decode, Rename(Map), Wakeup, Select, Drive, Execute, Commit. Each of the pipeline stages takes a single cycle to execute.
  2. The core supports all standard instructions of the RISC-V ISA for RV32I, RV64I and RV32M modes (Atomic instructions will be added by Christmas)
  3. Each instruction has its operands renamed in-order but issued out of order to the execution units. Commit is in-order.
  4. Register Renaming is done through a merged register file approach. Merged register files store both the architectural register values and speculated values. The number of architectural registers are 32 and the number of physical registers are 64. A buffer (register alias table) maintains the architectural register to physical register map.
  5. The Branch Predictor is a Tournament Branch predictor. It has Bimodal and Global predictors. More advanced BP schemes will be added shortly.
  6. The Functional Units are parameterised. The current design uses 2 Arithmetic and Logical Units, 1 Branch Unitand 1  Load Store Unit.
  7. The I-Cache and D-Cache use a PIPT scheme and will be changed to a VIPT scheme once the MMU is added. Each cache is nominally configured at 32KB. The cache is fully parameterised in terms of the size of the cache, associativity, number of blocks within a cache line, number of sets, etc. The caches are implemented using BRAMs provided in the Bluespec library. These BRAMs have a direct correlation to the FPGA based Block RAMs, easing the translation to an FPGA based design.
  8. This variant supports only the machine mode.

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